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ht37q70/60/50/40/30/20 4-channel music synthesizer mcu rev. 1.00 1 february 17, 2009 features operating voltage: 3.6v~5.5v (ht37q70/60) 3.3v~5.5v (ht37q50/40) 2.4v~5.5v (ht37q30/20) operating frequency: typical 11.059mhz oscillation modes for the oscillator clock f osc : crystal (11.059mhz) 1-pin rc oscillation typ. 11.059mhz built-in 8-bit mcu (ht-8) with 320 8 bits ram built-in 32k 16-bits to 256k 16-bits rom for program/data shared eight-level subroutine nesting two 8 bit timer and one 16 bit timer watchdog timer power-down and wake-up features for power saving operation 16-bit table read instructions for any bank/page read support 16 to 28 bidirectional i/o lines integrated 1-ch mono 16-bit dac converter integrated power amplifier four channel polyphonic synthesizer low voltage reset (tolerance 10%) external interrupt int external 2 timer clock input 4 or 8 touch switch input adpcm decoder bit manipulation instructions 63 powerful instructions all instructions in 1 or 2 machine cycles general description the device is an 8-bit high performance risc architec- ture microcontroller specifically designed for various music and adpcm applications. it provides an 8-bit mcu and 4-channel wavetable synthesizer. it has a in - tegrated 8-bit micro controller which controls the syn- thesizer to generate the melody by setting the special register. a power-down function is included to reduce power consumption. technical document application note ha0075e mcu reset and oscillator circuits application note selection table most features are common to all devices, the main feature distinguishing them are program memory capacity, i/o count, dac output, r2f input and package types. the following table summarizes the main features of each device. part no. vdd channel osc program rom ram i/o d/a power amp cr/f lvr package types HT37Q20 2.4v~ 5.5v 2+2 11.059 mhz 32k16bit 3208bit 16 1ch-mono 4 2.2v/ 3.3v 20/28sop ht37q30 64k16bit 20 8 2.2v/ 3.3v 28sop, 48ssop ht37q40 3.3v~ 5.5v 96k16bit 28 8 3.0v 28sop, 64qfp, 80lqfp ht37q50 128k16bit 28 8 ht37q60 3.6v~ 5.5v 192k16bit 28 8 3.3v ht37q70 256k16bit 28 8
block diagram pin assignment ht37q70/60/50/40/30/20 rev. 1.00 2 february 17, 2009
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. - 3 - + ' ' ' 4 0 1 2 3 - . 5 ' 4 - - 0 - - 1 - 2 - 3 - - - - . / 0 1 - 3 2 1 0 / . - 3 2
6 - + ' ' ' 4 ' 4 6 5 7 4 6 ' 8 ' 4 6 6 0 1 2 3 - . 6 6 . ' 4 2 2 0 2 2 1 2 2 2 3 2 - 2 2 . 3 / 3 3 0 3 3 1 3 2 3 3 3 - 3 3 . - / - - 0 - - 1 - 3 2 1 0 / . - 3 2 1 0 / - . - - - - 3 - 2

. - 3 6 6 6 - + 6 6 6 ' ' ' 4 ' 4 6 5 7 4 6 ' 8 ' 4 ' 4 0 1 2 3 - . 0 1 2 3 - . 6 6 6 6 6 6 6 . 6 6 6 6 6 6 6 6 6 6 6 6 6 3 - . 0 1 2 3 - . 0 1 2 3 - - . - - - - 3 - 2 6 6 6 6 6 6 - + ' ' ' 4 ' 4 6 5 7 4 6 ' 8 ' 4 . ' ' 8 0 8 8 1 8 2 8 3 8 - 8 8 . . ' 4 3 -3 3 .- /- - 0- - 1 - 3 2 1 0 / . - 3 2 1 0 / 1 1 . 2 / 2 2 0 2 2 1 2 2 2 3 2 - 2 2 . 3 / 3 3 0 3 3 1 3 2 3 3 2 3 - . 1 -1 31 21 11 1 01 1 / 2 0 2 2 1 2 2 2 3 2 - 2 - 3 2 1 0 / . - 3 2 1 0 / - . - - - - 3 - 2 - 1 - - 0 - - / 3 . 3 3 - 3 3 3 2 3 1 3 3 0 3 3 / 2 . . 0 / 0 0 0 0 0 1 0 2 0 3 0 - 0 0 . / 0 1 2 3 - . 1 / 1 1 0 1 1 1 1 2 1 3 1 - 1 2 . 2 / 2 6 6 6 6 6 6 6 6 6 6 6 - + ' ' ' 4 ' 4 6 5 3 - . 0 1 2 3 - . 0 1 2 3 - . ' ' 8 0 8 8 1 8 2 8 3 8 - 8 8 . 6 6 6 6 . ' 4 ' 4 ' 8 7 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 - - 0 - - 1 - 2 - 3 - - - - . / 0 1 - 3 2 1 0 / . - 3 2
- - + ' ' ' 4 ' 4 6 5 7 4 6 ' 8 ' 4 . 0 1 2 3 - . 6 6 . ' 4 - - 0 - - 1 - 2 - 3 - - - - . / 0 1 - 3 2 1 0 / . - 3 2
. - 3 . - 3 - + ' ' ' 4 0 1 2 3 - . 6 6 6 6 5 ' 4
pin assignment ht37q70/60 chip size: 2325 5155 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht37q70/60/50/40/30/20 rev. 1.00 3 february 17, 2009 9 . : . ; - 3 2 1 0 / . - 3 2 1 0 / - . - - - - 3 - 2 - 1 - - 0 - - / 3 . 1 . 2 / 2 2 0 2 2 1 2 2 2 3 2 - 2 2 . 3 / 3 3 0 3 3 1 3 2 3 3 3 - 3 - + 6 6 6 ' ' ' 4 ' 4 6 5 ' ' 8 0 8 8 1 8 2 8 3 8 - 8 8 . . ' 4 ' 4 ' 4 ' 4 ' 8 7 4 6 3 - . 0 1 2 3 - . 0 1 2 3 - .
ht37q50/40 chip size: 2325 4070 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht37q70/60/50/40/30/20 rev. 1.00 4 february 17, 2009 9 . : . ; - 3 2 1 0 / . - 3 2 1 0 / - . - - - - 3 - 2 - 1 - - 0 - - / 3 . 1 . 2 / 2 2 0 2 2 1 2 2 2 3 2 - 2 2 . 3 / 3 3 0 3 3 1 3 2 3 3 3 - 3 - + 6 6 6 ' ' ' 4 ' 4 6 5 ' ' 8 0 8 8 1 8 2 8 3 8 - 8 8 . . ' 4 ' 4 ' 4 ' 4 ' 8 7 4 6 3 - . 0 1 2 3 - . 0 1 2 3 - .
ht37q30 chip size: 2360 3325 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht37q70/60/50/40/30/20 rev. 1.00 5 february 17, 2009 9 . : . ; - 3 2 1 0 / . - - + 6 6 6 ' ' ' 4 ' 4 6 5 . ' 4 ' 4 ' 4 ' 4 ' 8 7 4 6 3 - . 0 1 2 3 - . 0 1 2 3 - . 3 2 1 0 / - . 2 . 3 / 3 3 0 3 3 1 3 2 3 3 3 - 3 3 . - / - - 0 - - 1 - 2 - 3 - - -
HT37Q20 chip size: 2230 2735 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht37q70/60/50/40/30/20 rev. 1.00 6 february 17, 2009 9 . : . ; - 3 - + 6 6 6 ' ' ' 4 ' 4 5 3 - . 3 - . 0 1 2 3 - . 2 - 0 - - 1 - 2 1 0 / . - 3 2 1 - 3 - - - - . / 0
pad coordinates ht37q70/60 unit: m pad no. x y pad no. x y 1 1012.900 531.665 26 386.650 2427.900 2 1012.900 630.665 27 481.650 2427.900 3 1012.900 729.665 28 584.650 2427.900 4 1013.195 899.560 29 745.620 2383.710 5 1013.195 999.560 30 847.745 2391.950 6 1013.195 1099.560 31 1012.900 2393.440 7 998.595 1206.810 32 1012.900 2290.440 8 998.595 1311.415 33 1012.900 2195.440 9 971.945 1412.145 34 1012.900 2092.440 10 974.895 1568.917 35 1012.900 1997.440 11 975.025 1685.445 36 1012.900 1894.440 12 975.025 1790.745 37 1012.900 1799.440 13 1057.200 2363.935 38 1012.900 1696.441 14 954.200 2363.935 39 1012.900 1601.440 15 822.375 2389.970 40 1012.900 1498.440 16 715.426 2389.970 41 1012.900 1403.440 17 608.475 2389.970 42 1012.900 1300.440 18 480.425 2389.970 43 1012.900 1205.440 19 373.474 2389.970 44 1012.900 1102.440 20 266.525 2389.970 45 1012.900 1007.440 21 112.350 2427.900 46 1012.900 904.440 22 9.350 2427.900 47 1012.900 809.440 23 85.650 2427.900 48 1012.900 708.240 24 188.650 2427.900 49 1012.900 605.240 25 283.650 2427.900 50 1012.900 510.240 ht37q50/40 unit: m pad no. x y pad no. x y 1 1012.900 9.835 26 386.650 1886.400 2 1012.900 89.165 27 481.650 1886.400 3 1012.900 188.165 28 584.650 1886.400 4 1013.195 358.060 29 745.620 1842.210 5 1013.195 458.060 30 847.745 1850.450 6 1013.195 558.060 31 1012.900 1851.940 7 998.595 665.310 32 1012.900 1748.940 8 998.595 769.915 33 1012.900 1653.940 9 971.945 870.645 34 1012.900 1550.940 10 974.895 1027.417 35 1012.900 1455.940 11 975.025 1143.945 36 1012.900 1352.940 12 975.025 1249.245 37 1012.900 1257.940 13 1057.200 1822.435 38 1012.900 1154.940 14 954.200 1822.435 39 1012.900 1059.940 15 822.375 1848.470 40 1012.900 956.940 16 715.426 1848.470 41 1012.900 861.940 17 608.475 1848.470 42 1012.900 758.940 18 480.425 1848.470 43 1012.900 663.940 19 373.474 1848.470 44 1012.900 560.940 20 266.525 1848.470 45 1012.900 465.940 21 112.350 1886.400 46 1012.900 362.940 22 9.350 1886.400 47 1012.900 267.940 23 85.650 1886.400 48 1012.900 166.740 24 188.650 1886.400 49 1012.900 63.740 25 283.650 1886.400 50 1012.900 31.260 ht37q70/60/50/40/30/20 rev. 1.00 7 february 17, 2009
ht37q30 unit: m pad no. x y pad no. x y 1 1031.100 306.920 21 1031.340 405.950 2 1031.100 207.920 22 1031.340 508.950 3 1031.100 102.485 23 1031.340 603.950 4 1038.550 69.700 24 1031.340 706.950 5 1038.550 156.700 25 1031.340 801.950 6 1038.550 243.700 26 1031.340 904.950 7 1016.795 336.210 27 1031.340 999.950 8 1016.795 442.465 28 1031.340 1102.950 9 1028.020 537.520 29 1031.340 1197.950 10 1030.970 688.142 30 1031.340 1300.950 11 1031.100 804.670 31 1031.340 1395.950 12 1031.100 909.970 32 1031.340 1498.950 13 1075.000 1449.785 33 777.240 1513.750 14 972.400 1449.785 34 674.240 1513.750 15 840.575 1475.820 35 579.240 1513.750 16 733.626 1475.820 36 476.240 1513.750 17 626.675 1475.820 37 381.240 1513.750 18 498.625 1475.820 38 280.190 1513.750 19 391.674 1475.820 39 177.190 1513.750 20 284.725 1475.820 40 82.190 1513.750 HT37Q20 unit: m pad no. x y pad no. x y 1 957.220 1218.355 15 305.520 1218.355 2 966.120 956.015 16 966.120 813.375 3 966.120 853.015 17 966.120 916.375 4 966.120 758.015 18 966.120 1011.375 5 966.120 580.625 19 966.120 1114.375 6 966.120 679.625 20 966.120 1209.375 7 966.120 785.055 21 757.770 1218.355 8 964.415 931.730 22 662.770 1218.355 9 964.415 1018.730 23 559.770 1218.355 10 964.415 1105.730 24 561.220 1218.355 11 962.015 1202.625 25 664.220 1218.355 12 647.840 1180.218 26 759.220 1218.355 13 534.220 1183.955 27 862.220 1218.355 14 427.120 1188.955 ht37q70/60/50/40/30/20 rev. 1.00 8 february 17, 2009
pad description ht37q70, ht37q60, ht37q50, ht37q40 pad name i/o configuration option function vdd positive digital power supply vdd_dac positive dac circuit power supply vdd_amp positive power amp. power supply vss negative digital power supply, ground vss_dac negative dac power supply, ground vss_amp negative amp power supply, ground pa0~pa4 pa5/int pa6/tmr0 pa7/tmr1 i/o pull-high wake-up bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if all pins on this port have pull-high resistors. pins pa5, pa6 and pa7 are pin-shared with int , tmr0 and tmr1, respectively. pb0~pb7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pc0/k0~ pc7/k7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pins pc0 ~ pc7 are pin-shared with k0 and k7, respectively (k0~k7 are cr/f function). pd0/rcout pd1/rr pd2/rc pd3/cc i/o pull-high bi-directional 4-bit i/o port. software instructions determined the cmos out- put or schmitt trigger with a pull-high resistor (determined by pull-high option: by option). pins pd0~pd3 are pin-shared with cr/f osc input pins rcout, rr, rc and cc. rcout, rr, rc and cc control pin for cr/f function. rch o audio right channel output sp1, sp0 o power amp. output pins aud_in i power amp. input pin vbias o power amp. voltage bias reference pin. res i schmitt trigger reset input, active low osc1 osc2 i o crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys - tem clock at 1/8 frequency. nc no connection note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins can be selected to have pull-high resistors. 3. because the two timers are used by midi the external timer pin functions are disabled. ht37q70/60/50/40/30/20 rev. 1.00 9 february 17, 2009
ht37q30 pad name i/o configuration option function vdd positive digital power supply vdd_dac positive dac circuit power supply vdd_amp positive power amp. power supply vss negative digital power supply, ground vss_dac negative dac power supply, ground vss_amp negative amp power supply, ground pa0~pa4 pa5/int pa6/tmr0 pa7/tmr1 i/o pull-high wake-up bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if all pins on this port have pull-high resistors. pins pa5, pa6 and pa7 are pin-shared with int , tmr0 and tmr1, respectively. pc0/k0~ pc7/k7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pins pc0 ~ pc7 are pin-shared with k0 and k7, respectively (k0~k7 are cr/f function). pd0/rcout pd1/rr pd2/rc pd3/cc i/o pull-high bi-directional 4-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by pull-high option: by option). pins pd0~pd3 are pin-shared with cr/f osc input pins rcout, rr, rc and cc. rcout, rr, rc and cc control pin for cr/f function. rch o audio right channel output sp1, sp0 o power amp. output pins aud_in i power amp. input pin vbias o power amp. voltage bias reference pin. res i schmitt trigger reset input, active low osc1, osc2 i o crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys - tem clock at 1/8 frequency. nc no connection note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins can be selected to have pull-high resistors. 3. because the two timers are used by midi the external timer pin functions are disabled. ht37q70/60/50/40/30/20 rev. 1.00 10 february 17, 2009
HT37Q20 pad name i/o configuration option function vdd positive digital power supply vdd_dac positive dac circuit power supply vss negative digital power supply, ground vss_dac negative dac power supply, ground pa0~pa4 pa5/int pa6/tmr0 pa7/tmr1 i/o pull-high wake-up bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if all pins on this port have pull-high resistors. pins pa5, pa6 and pa7 are pin-shared with int , tmr0 and tmr1, respectively. pc0/k0~ pc3/k3 i/o pull-high bidirectional 4-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if all pins on this port have pull-high resistors. pins pc0 ~ pc3 are pin-shared with k0 and k3, respectively (k0~k3 are cr/f function). pd0/rcout pd1/rr pd2/rc pd3/cc i/o pull-high bi-directional 4-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by pull-high option: by option). pins pd0~pd3 are pin-shared with cr/f osc input pins rcout, rr, rc and cc. rcout, rr, rc and cc control pin for cr/f function. rch o audio right channel output res i schmitt trigger reset input, active low osc1 osc2 i o crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys- tem clock at 1/8 frequency. nc no connection note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins can be selected to have pull-high resistors. 3. because the two timers are used by midi the external timer pin functions are disabled. absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +5.5v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0 . 3v to v dd +0.3v operating temperature .......................... 20 cto70 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under
absolute maximum ratings
may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht37q70/60/50/40/30/20 rev. 1.00 11 february 17, 2009
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f osc =11.059mhz for ht37q30/20 2.4 3.0 5.5 v f osc =11.059mhz for ht37q50/40 3.3 4.5 5.5 v f osc =11.059mhz for ht37q70/60 3.6 4.5 5.5 v i dd operating current (crystal osc or rc osc) 3v no load, f osc =8mhz~12.8mhz, dac disable 28ma 5v 816ma i stb1 standby current (wdt disable) 3v no load, system halt, wdt disable 1 a 5v 2 a i stb2 standby current (wdt enable) 3v no load, system halt, wdt enable 5 a 5v 10 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol i/o port segment logic output sink current 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh i/o port segment logic output source current 3v v oh =0.9v dd 2 4 ma 5v 5 8 ma r ph pull-high resistance of i/o ports 3v 20 60 100 k 5v 10 30 50 k v lvr low voltage reset voltage 5v lvr 2.2v option 2.0 2.2 2.4 v lvr 3.0v option 2.7 3.0 3.3 v lvr 3.3v option 3.0 3.3 3.6 v i o aud current source v oh =0.9v dd 3 ma i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma p o internal amp output power 3v (thd+n)/s 1%, r l =8 v in =1khz sinewave 90 mw (thd+n)/s 10%, r l =8 v in =1khz sinewave 125 mw 5v (thd+n)/s 1%, r l =8 v in =1khz sinewave 385 mw (thd+n)/s 10%, r l =8 v in =1khz sinewave 490 mw note: lvr 3.0v only applies to ht37q50 and ht37q40. ht37q70/60/50/40/30/20 rev. 1.00 12 february 17, 2009
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f osc oscillator clock (crystal osc/rc osc) 2.4v~5.5v 8000 11059 12800 khz 3.3v~5.5v 8000 11059 12800 3.6v~5.5v 8000 11059 12800 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t lvr low voltage width to reset 0.25 1.00 2.00 ms note: t sys = 1/f sys f sys =f osc /2 characteristics curves ht37q70/60/50/40/30/20 rev. 1.00 13 february 17, 2009

(thd+n) vs. output power r load =8,v in =1khz sinewave for 3.0v r load =8,v in =1khz sinewave for 5.0v ht37q70/60/50/40/30/20 rev. 1.00 14 february 17, 2009 . . 1 . - . . 1 - . > 1 . > - . > . > . 1 . > . - . > . - 1 . - . 1 . . . - . . 1 . . - 1 ! & 9 " ; ? . . 1 . - . . 1 - . > 1 . > - . > . > . 1 . > . - . > . - 1 . - . 1 . . . - . . 1 . . - 1 ! & 9 " ; ?
ht37q70/60/50/40/30/20 rev. 1.00 15 february 17, 2009 system architecture a key factor in the high-performance features of the holtek range of music type microcontrollers is attrib - uted to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the in - struction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch de - cisions, etc. the internal data path is simplified by mov - ing data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with addi - tional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crys- tal/resonator or rc oscillator. the oscillator frequency divided by 2 is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cy - cles, the pipelining structure of the microcontroller en - sures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. when the rc oscillator is used, osc2 is freed for use as a t1 phase clock synchronizing pin. this t1 phase clock has a frequency of f osc /8 with a 1:3 high/low duty cycle. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by pro - grammers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as
jmp
or
call
, that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is se- lected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. ) # > 9 ; + @ > 9 ; ) # > 9 a ; + @ > 9 ; ) # > 9 a - ; + @ > 9 a ; a a - * ( 7 9 ( b c ( - ; !

-
3
2

-
3
2

-
3
2 system clocking and pipelining ) # > + @ > ) # > - ) # ! - 3 2 1 + % b d ' : e - 5 f % % + % b % e - 5 f d d 6 + @ > - ) # > 3 ) # > + @ > ) # > 0 instruction fetching
ht37q70/60/50/40/30/20 rev. 1.00 16 february 17, 2009 when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack can have 8 levels depending upon which option is selected and is neither part of the data nor part of the program space, and is neither readable nor writable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writable. at a subroutine call or interrupt acknowledge signal, the contents of the pro - gram counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is re - stored to its previous value from the stack. after a de - vice reset, the stack pointer will point to the top of the stack. mode program counter b17~b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 00000 0000000000000 timer/event counter 0 overflow 00000 0000000001000 timer/event counter 1 overflow 00000 0000000001100 timer counter 2 overflow 00000 0000000010000 ercoci interrupt 00000 0000000010100 adpcm interrupt 00000 0000000011000 skip program counter + 2 (within current bank) loading pcl p17~p13 p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp1.4~bp1.0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s17~s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: p17~p8: program counter bits @7~@0: pcl bits #12~#0: instruction code address bits bp1.4~bp1.0: rom bank pointer s17~s0: stack register bits for the ht37q70/60, the program counter is 18 bits wide, i.e. from b17~b0. for the ht37q50/40, the program counter is 17 bits wide, i.e. from b16~b0, therefore the b17 column in the table is not applicable. for the ht37q30, the program counter is 16 bits wide, i.e. from b15~b0, therefore the b17 and b16 the col - umns in the table are not applicable. for the HT37Q20, the program counter is 15 bits wide, i.e. from b14~b0, therefore the b17, b16 and b15 the columns in the table are not applicable.
ht37q70/60/50/40/30/20 rev. 1.00 17 february 17, 2009 if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in- struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper- ations may result in carry, borrow or other status changes, the status register will be correspondingly up- dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the type of memory is the mask rom memory. it offer the most cost effective solu - tions for high volume products. structure the program memory has a capacity of 256k by 16, 192k by 16, 128k by 16, 96k by 16, 64k by 16 or 32k by 16 bits depending upon which device is selected. the program memory is addressed by the program counter and rom bank point, and also contains general data, wave table data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialization. after a device reset is initiated, the program will jump to this location and begin execu - tion. location 004h this vector is used by the external interrupt. if the ex - ternal interrupt pin on the device goes low, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this vector is reserved for the timer/event counter 0 interrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in- terrupt is enabled and the stack is not full, the program begins execution at location 008h. location 00ch this vector is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and if the in- terrupt is enabled and the stack is not full, the program begins execution at location 00ch. location 010h this vector is reserved for the timer counter 2 inter - rupt service program. if a timer interrupt results from a timer counter 2 overflow, and if the interrupt is en - abled and the stack is not full, the program begins ex - ecution at location 0010h. location 014h this vector is reserved for the ercoci interrupt ser - vice program. if an external rc oscillation converter interrupt results from an external rc oscillation con - verter interrupt is activated, and the stack is not full, the program begins execution at location 0014h. location 018h this vector is reserved for the adpcm interrupt service program. if a adpcm interrupt results, and if the inter - rupt is enabled and the stack is not full, the program begins execution at location 0018h. * % , * % , - * % , 3 * % ,
! ( * * 8 ( *
ht37q70/60/50/40/30/20 rev. 1.00 18 february 17, 2009 . 2 5 ' + @ ! '
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+ , ! '
+ , - ! ' . 5 + ! ' ! ' 8 * g 3 9 8 e 2 d . f c e f g e ) 5 f ; . 2 5 ' + @ ! '
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ht37q70/60/50/40/30/20 rev. 1.00 19 february 17, 2009 look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the three table pointer registers, tblp, tbmp and tbhp. this three registers define the ad - dress of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory or last program memory page in the specific bank which defined by bank point register as bp1 using the
tabrdc[m]
or
tabrdl [m]
instruc - tions, respectively. when these instructions are exe - cuted, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any un - used bits in this transferred higher order byte will have uncertain values. the following diagram illustrates the addressing/data flow of the look-up table: table program example the following example shows how the table pointer and table data is defined and retrieved from the ht37q70/60/50/30/40/20 microcontroller. this exam - ple uses raw table data located in the last page which is stored there using the org and rombank statement. the value at this org statement is
3f00h
which re - fers to the start address of the last page within the pro - gram memory of the ht37q70/60/50/40/30/20 microcontroller. the table pointer is setup here to have an initial value of
06h
. this will ensure that the first data read from the data table will be at the program memory address
3f06h
or 6 locations after the start of the last page in selected rombank. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the
tabrdl [m]
instruction is executed. because the tblh register is a read-only register and cannot be re - stored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instruc - tions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recom - mended that simultaneous use of the table read instruc - tions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
8 5
8
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% & 8 (

8 % instruction table location bits b17~b13 b12~b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] tbhp1_1~tbmp1_5 tbmp1_4~tbmp1_0 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] bp1_4~bp1_0 11111 @7 @6 @5 @4 @3 @2 @1 @0 table location note: @7~@0: table pointer lower-order bits are tblp1 [7:0] b17~b0: current program rom table address a [17:0] tbmp1_4~tbmp1_0: tbmp1 bit 4 ~0 tbhp1_1~tbmp1_5: tbhp1 (bit 1 ~0) to tbmp1 (bit7 ~5) bp1_4 ~bp1_0: bits of bank bp1 bit0~4 for the ht37q70/60, the table address location is 18 bits wide, i.e. from b17~b0. for the ht37q50/40, the table address location is 17 bits wide, i.e. from b16~b0. for the ht37q30, the table address location is 16 bits wide, i.e. from b15~b0. for the HT37Q20, the table address location is 15 bits wide, i.e. from b14~b0.
ht37q70/60/50/40/30/20 rev. 1.00 20 february 17, 2009 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 tempreg3 db ? ; temporary register #3 tempreg4 db ? ; temporary register #4 : : mov a,01h ; set rom bank 1 point mov bp1,a mov a,06h ; initialise table pointer mov tblp1,a ; to the last page clr tbmpl clr tbhpl : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address
3f06h
transferred to ; tempreg1 and tblh dec tblp1 ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address
3f05h
transferred to ; tempreg2 and tblh ; in this example the data
1ah
is transferred to ; tempreg1 and data
0fh
to register tempreg2 ; the value
00h
will be transferred to the high byte ; register tblh : : mov a,04h ; initialise table pointer low byte mov tblp1,a ; mov a,3fh ; initialise table pointer middle byte mov tbmp1,a mov a,00h ; initialise table pointer high byte mov tbhp1,a tabrdc tempreg3 ; : : rombank 1 romsumvalue1; sets rombank 1 initial address of last page ;(for ht37q70/60/50/40/30/20) romsumvalue1 .section at 1f00h code dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
ht37q70/60/50/40/30/20 rev. 1.00 21 february 17, 2009 rom bank pointer (2dh) the program memory is organized into 32/24/16/12/8/4 banks for ht37q70/60/50/40/30/20 and each bank into 8192 16 bits of program rom. bp1.7~bp1.0 is used as the bank pointer. after an instruction has been executed to write data to the bp1 register to select a different bank, note that the new bank will not be selected immediately. it is until the instruction
jmp
or
call
or interrupt has completed execution that the bank will be actually selected. register bit no. function bp1 (2dh) 0~7 00000000b= select rom bank0 (0000h~1fffh) 00000001b= select rom bank1 (2000h~3fffh) 00000010b= select rom bank2 (4000h~5fffh) 00000011b= select rom bank3 (6000h~7fffh) : 00011110b= select rom bank30 (3c000h~3dfffh) 00011111b= select rom bank31 (3e000h~3ffffh) note: for the ht37q70/60, the rom bank point register is 5 bits wide effectively, i.e. from b4~b0. for the ht37q50/40, the rom bank point register is 4 bits wide effectively, i.e. from b3~b0. for the ht37q30, the rom bank point register is 3 bits wide effectively, i.e. from b2~b0. for the HT37Q20, the rom bank point register is 2 bits wide effectively, i.e. from b1~b0. ram data memory the ram data memory is a volatile area of 8-bit wide ram internal memory and is the location where tempo - rary information is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed loca- tions and are necessary for correct operation of the de- vice. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of ram data memory is reserved for general purpose use. all locations within this area are read and write accessi- ble under program control. structure the ram data memory is subdivided into 2 banks, known as bank 0 and bank 1, all of which are imple - mented in 8-bit wide ram. most of the ram data mem - ory is located in bank 0 which is also subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the data memory is the address
00h
. registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. bank 1 of the ram data memory is located at address
60h
. the ram data memory is designed with 320 8 bits with 2 ram banks. there are two ram bank pointers (rbp1 and rbp2 ) control bank 0~1 (rbp1.0/rbp2.0) the data memory is designed with 256 bytes and di- vided into five functional groups: special function regis- ters (00h~1fh), music synthesis controller registers (20h~2fh), adpcm decoder controller register (30h~35h), the other function (35h~5fh) and general purpose data memory (60h~ffh). they are also indirectly accessible through memory pointer registers mp0, mp1and mp2, where mp1/mp2 can deal with all banks of data memory but mp0 deal with bank0 data memory only. rbp1 (04h) bit0 control mp1 rbp2 (2fh) bit0 control mp2 general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. the bank 0 data memory areas can handle arithmetic, logic, incre - ment, decrement and rotate operations directly. by us - ing the
set [m].i
and
clr [m].i
instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipu - lation in the data memory. ! ! . . 5 1 ) 5 . 5 . ) ) 5 $ % & $ % & ' h ! 9 . 8 ; h ! 9 . 8 ; bank 0~bank 1 ram data memory structure
ht37q70/60/50/40/30/20 rev. 1.00 22 february 17, 2009 8 - i % i 5 6
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i i ) ) h h 8 h - . . 5 . 5 . - 5 . 3 5 . 2 5 . 1 5 . 5 . 0 5 . 5 . / 5 . 5 . 8 5 . 5 . 5 . + 5 . ) 5 . 5 5 - 5 3 5 2 5 1 5 5 0 5 5 / 5 5 8 5 5 5 + 5 ) 5 - . 5 - 5 - - 5 - 3 5 - 2 5 - 1 5 - 5 - 0 5 . . 8 %
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8 8 - 5 - / 5 - 5 - 8 5 - 5 - 5 3 . 5 3 5 3 - 5 3 3 5 3 2 5 3 1 5 3 5 3 0 5 3 5 3 / 5 3 5 3 8 5 3 5 3 5 3 + 5 3 ) 5 2 . 5 2 5 2 - 5 2 3 5 2 2 5 2 1 5 2 5 2 0 5 2 5 2 / 5 2 5 2 8 5 2 5 2 5 2 + 5 2 ) 5 1 . 5 1 5 1 - 5 1 3 5 1 2 5 1 1 5 1 ) 5 - ) 5 ) ) 5 . 5 - + 5 h ! 9 3 - . 8 d . 8 @ - 8 * ; data memory structure special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value
00h
. although the special pur - pose data memory registers are located in bank 0, they will still be accessible even if the bank pointer has se - lected bank 1.
ht37q70/60/50/40/30/20 rev. 1.00 23 february 17, 2009 special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the ram data memory area. these registers ensure correct op - eration of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as i/o data control. the location of these registers within the ram data memory begins at the address
00h
. indirect addressing register iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1/mp2. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1/mp2 register can access data from both bank 0 and bank 1. using mp1 or mp2 are selected by dacc.7. as the indirect ad - dressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of
00h
and writing to the registers indi - rectly will result in no operation. memory pointer mp0, mp1, mp2 three memory pointers, known as mp0, mp1 and mp2 are provided. these memory pointers are physically im - plemented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to address and track data. when any operation to the relevant indirect addressing regis - ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0 only, while mp1/mp2 and iar1 are used to access data from both bank 0 and bank 1. using mp1 or mp2 are selected by dacc.7. example the following example shows how to clear general purpose data memory of bank0 by using mp0 and bank0~bank1 by using mp1 and mp2 code .section at 0 code org 00h ram0test: mov a,60h mov mp0,a ; loaded with first ram address loop0: clr iar0 ; clear the data at address defined by mp0 clr wdt siz mp0 ; increase mp0, and skip out if mp0 is
0
jmp loop0 : ram1test: clr dacc.7 ; access data to iar1 by mp1 clr rbp1 ; clear ram bank pointer 1 ram1_mp1: mov a,rbp1 ; load rbp1 data, and check if rbp1 is
25
xor a,25 sz zero ; jump to exit loop if rbp1 is
2
jmp ram1test_exit mov a,60h ; loaded with first ram address to mp1 mov mp1,a loop1: clr wdt clr iar1 ; clear the data at address defined by mp1 siz mp1 ; increase mp1, and skip out if mp1 is
0
jmp loop1 inc rbp1 ; increase rbp1 jmp ram1_mp1 ram1test_exit: : ram2test: set dacc.7 ; access data to iar1 by mp2 clr rbp2 ; clear ram bank pointer 2
ht37q70/60/50/40/30/20 rev. 1.00 24 february 17, 2009 ram1mp2: mov a,rbp2 xor a,25 sz zero ; jump to exit loop if rbp2 is
2
jmp ram2test_exit mov a,60h ; loaded with first ram address to mp2 mov mp2,a loop2: clr wdt clr iar1 ; clear the data at address defined by mp2 siz mp2 ; increase mp2, and skip out if mp2 is
0
jmp loop2 inc rbp2 ; increase rbp2 jmp ram1mp2 ram2test_exit: : bank pointer rbp1, rbp2 the ram data memory is divided into 2 banks, known as bank 0 to bank 1. selecting the required data memory area is achieved using the ram bank pointers which are rbp1 and rbp2. the rbp1 and rbp2 match up with mp1 and mp2 respectively. if data in bank 0 is to be ac - cessed, then the rbp registers must be loaded with the value
00
, while if data in bank 1 is to be accessed, then the rbp registers must be loaded with the value
01
. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irre - spective of the value of the bank pointer. the rbp1 and rbp2 register is located at memory location 60h in bank 0 to bank 1 and can only be accessed indirectly using two memory pointers mp1 and mp2 and the indi- rect addressing register iar1 will always access data from bank 0 to bank 1. the data memory is initialized to bank 0 to bank 1 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank re- mains unaffected. it should be noted that special func - tion data memory is not affected by the bank selection, which means that the special function registers can be accessed from within bank 0 to bank 1. directly ad - dressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. register bit no. function rbp1 0 ram bank point 1 select 0= select ram bank0 1= select ram bank1 1~7 unused bit rbp1 (04h) register bit no. function rbp2 0 ram bank point 2 select 0= select ram bank0 1= select ram bank1 1~7 unused bit rbp2 (2fh) note: using mp1 or mp2 are selected by dacc.7. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro- grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp1, tbmp1, tbhp1, tblh these seven special function registers are used to con - trol operation of the look-up table which is stored in the program memory. tblp1, tbmp1 and tbhp1 are the table pointer and indicate the location where the table data is located. their value must be setup before any ta - ble read commands are executed. their value can be changed, for example using the
inc
or
dec
instruc - tions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the ta - ble data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defined location.
ht37q70/60/50/40/30/20 rev. 1.00 25 february 17, 2009 watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera- tions related to the status register may give different re- sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the
clr wdt
or
halt
in- struction. the pdf flag is affected only by executing the
halt
or
clr wdt
instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the
clr wdt
instruction. pdf is set by executing the
halt
instruction. to is cleared by a system power-up or executing the
clr wdt
or
halt
instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control registers intc, intch the two 8-bit registers, known as the intc and intch register which control the operation of both external and internal timer, cr/f and adpcm interrupts, and by set- ting various bits within this register using standard bit manipulation instructions, the enable/disable function of the external and timer, cr/f and adpcm interrupts can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/dis- able and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is en- tered to disable further interrupt and is set by executing the
reti
instruction. note: in situations where other interrupts may require servicing within present interrupt service rou - tines, the emi bit can be manually set by the pro - gram after the present interrupt service routine has been entered.
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ht37q70/60/50/40/30/20 rev. 1.00 26 february 17, 2009 timer/event counter registers tmr0h, tmr0l, tmr1l, tmr2l, tmr0c, tmr1c, tmr2c ht37q70/60/50/40/30/20 contains two 8-bit and a 16-bit timer/event counters which has an associated register known as tmr0h and tmr0l. are the location where the timer s 16-bit value is located.tmr1l and tmr2l are the location where the timer s 8-bit value is located. an associated control register, known as tmr0c, tmr1c and tmr2c contains the setup infor - mation for the timer. input/output ports and control registers pa, pb, pc, pd, pac, pbc, pcc, pdc within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc and pd. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc and pdc, also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the con- trol register must be set high, for an output it must be set low. during program initialization, it is important to first setup the control registers to specify which pins are out- puts and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits us- ing the
set [m].i
and
clr [m].i
instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control reg - isters during normal program operation is a useful fea - ture of these devices. d/a converter registers dah, dal, dacc ht37q70/60/50/40/30/20 provide one 16-bit d/a con - verters. the correct operation of the d/a requires the use of two data registers, and a control register. it con - tain a 16-bit d/a converter, there are two data registers, a high byte data register known as dah, and a low byte data register known as dal. these are the register lo - cations where the digital value is placed before the com - pletion of a digital to analog conversion cycle. the configuration of the d/a converter is setup via the con - trol register dacc. wavetable function registers channel_number, freq_number_h, freq_number_l, repeat_number_h, repeat_number_l, volume_control, l_vol, r_vol ht37q70/60/50/40/30/20 contains wavetable synthe - sizer function. the ht37q70/60/50/40/30/20 has a built-in 8 output channels. channel_number is channel number selection. freq_number_h and freq_number_l are used to define the output speed of the pcm file. start_address_h and start_address_l is setup for the start address of the pcm code before wavetable function implement. the repeat number reg - ister as known repeat_number_h and re - peat_number_l are used to define the address which is the repeat point of the sample. when the repeat number is defined, it will be output from the start code to the end code once and always output the range be - tween the repeat address to the end code (80h) until the volume become close. it provides the left and right vol - ume control independently. the 10-bit left and right vol - ume are controlled by volume_control, l_vol, and r_vol respectively. the volume_control contain both left and right volume some bit of high byte. adpcm function registers adr, xspl, xsph, adpc, adps ht37q70/60/50/40/30/20 contains adpcm decoder function. the must set initial value of register known as xspl and xsph before implementing adpcm decoder procedure. there are two 4-bit adpcm encode data of adr. the data of adr implement via adpcm decoder, and output 8-bit pcm data which is synthesized by midi synthesizer. the adpc is the control register for the adpcm de - coder. the adps is the status register for the adpcm decoder. cr/f converter registers ascr, tmrah, tmral, rcoccr, tmrbh, tmrbl, rcocr there are 8 analog switch lines in the microcontroller for k0~k7 for ht37q70/60/50/40/30, except HT37Q20 which only have 4 analog switch lines for k0~k3 and a corresponding analog switch control registers known as ascr. the rc oscillation converter contains two 16-bit programmable count-up counters and the timer a clock source may come from the system clock (f sys =f osc /2) or system clock/4 (f osc /8). there are two data registers, a high byte data register known as tmrah, and a low byte data register known as tmral. the timer b clock source may come from the external rc oscillator. there are two data registers, a high byte data register known as tmrbh, and a low byte data register known as tmrbl. there are two control and status registers known as rcoccr and rcocr.
ht37q70/60/50/40/30/20 rev. 1.00 27 february 17, 2009 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. de - pending upon which device or package is chosen, the microcontroller range provides from 16 to 28 bidirectional input/output lines labeled with port names pa, pb, pc and pd. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction
mov a,[m]
, where m denotes the port ad - dress. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, i/o pins pa~pd, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via pa~pd option respectively, located in the configuration. the pull-high resistors are implemented using weak pmos transistors. port a wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is im - portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the pa0~pa7 pins from high to low. after a halt instruc - tion forces the microcontroller into entering the power down mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that pins pa0 to pa7 can be selected individually to have this wake-up feature using an pa wake up option, located in the con - figuration. i/o port control registers each i/o port have their own control register, known as pac, pab, pcc and pdc, which control the input/out - put configuration. with this control register, each pa~pd i/o pin with or without pull-high resistors can be recon - figured by pull-hi option control. pins pa~pd ports are directly mapped to a bit in its associated port control reg - ister. for the i/o pin to function as an input, the corre - sponding bit of the control register must be written as a
1
. this will then allow the logic state of the input pin to be directly read by instructions. when the correspond - ing bit of the control register is written as a
0
, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro- gram control. external interrupt input the external interrupt pin, int , is pin-shared with the i/o pin pa5. to use the pin as an external interrupt in - put the correct bits in the pa share pin option must be selected. the pin must also be setup as an input by setting the appropriate bit in the port control register. a pull-high resistor can also be selected via the appro - priate port pull-high option.
ht37q70/60/50/40/30/20 rev. 1.00 28 february 17, 2009 cr/f analog switch inputs the ht37q70/60/50/40/30 have 8 cr/f converter in - puts. all of these analog inputs are pin-shared with pc0 to pc7. if these pins are to be used as cr/f ana - log switch inputs and not as normal i/o pins then the corresponding bits in the option,
pc0~7 share pin configuration
. the HT37Q20 have 4 cr/f converter inputs. all of these analog inputs are pin-shared with pc0 to pc3. if these pins are to be used as cr/f ana - log switch inputs and not as normal i/o pins then the corresponding bits in the configuration,
pc0~3 share pin configuration
. cr/f oscillator pin the ht37q70/60/50/40/30/20 have 4 cr/f oscillator pins. all of these cr/f oscillator pin are pin-shared with pd0 to pd3. if these pins are to be used as cr/f oscil - lator pins and not as normal i/o pins then the corre - sponding bits in the option,
pd0~3 share pin option
. i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the user program, one of the first things to con - sider is port initialization. after a reset, the pa~pd data register and pac~pdc port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been se - lected. if the pac port control register, is then pro - grammed to setup some pins as outputs, these output pins will have an initial high output value unless the as - sociated pa port data register is first programmed. se - lecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the
set [m].i
and
clr [m].i
instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. 7 i 8 " # ! $ " $ " * 7 ! " * ! * ! * ! ' ' l m l l m l 8 8 input/output port

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ht37q70/60/50/40/30/20 rev. 1.00 29 february 17, 2009 timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices contain two count-up timers 8-bit capacity and one count-up timers 16-bit capacity. as the timer 0 / 1 has three different oper - ating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. but the timer 2 only be con - figured to operate as a general timer. the provision of an internal prescaler to the clock circuitry of some of the timer/event counters gives added range to the timer 1 / 2. there are three types of registers related to the timer/event counters 0. the first two register contain the actual high and low byte value of the timer and into which an initial value can be preloaded. there are two types of registers related to the timer/event counters 1 / 2. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and deter - mines how the timer is to be used. the timer/event counter 0 can have the timer clock configured to come from the internal clock source. the clock source is f osc /8.in addition, the timer clock source of timer/event counter 0 can also be configured to come from an inter - nal rc 12khz. an external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer pin, known as tmr0 or tmr1. these external timer pins are pin-shared with other i/o pins. depending upon the condition of pa share pin op - tion, each high to low, or low to high transition on the ex - ternal timer input pin will increment the counter by one.
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ht37q70/60/50/40/30/20 rev. 1.00 30 february 17, 2009 configuring the timer/event counter input clock source the internal timer s clock can originate from various sources, depending upon timer is chosen. the system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. for timer/event counter 0, these system clock timer source is selected by tmr0c.5. for timer/event counter 1, 2 this system clock timer source is first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits t1psc0~t1psc2. an external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer pin, known as tmr0 or tmr1. these external timer pins are pin-shared with other i/o pins. depending upon the condition of pa share pin op - tion, each high to low, or low to high transition on the ex - ternal timer input pin will increment the counter by one. timer registers tmr0h/tmr0l, tmr1, tmr2 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. for the 8-bit timer, this register is known as timer/event counter 1/2. in the case of the 16-bit timer, a pair of 8-bit registers are re- quired to store the 16-bit timer values. these are known as tmr1l/tmr1h. the value in the timer registers in- creases by one each time an internal clock pulse is re- ceived or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer or ffffh for the 16-bit timers, at which point the timer overflows and a timer internal interrupt signal is generated. the timer value will then be reset with the ini - tial preload register value and continue counting. note that to achieve a maximum full range count of ffh for the 8-bit timer or ffffh for the 16-bit timers, the preload registers must first be cleared to all zeros. it should be noted that after power-on, the preload regis - ters will be in an unknown condition. note that if the timer/event counters are in an off condition and data is written to their preload registers, this data will be im - mediately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will re - main in the preload register and will only be written into the actual counter the next time an overflow occurs. note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. the 16-bit timer/event counter have contained both low byte and high byte timer registers, accessing these registers is carried out in a specific way. it must be noted that when using instructions to preload data into the low byte register, namely tmr0l, the data will only be placed in a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only carried out when a write to its asso- ciated high byte register, namely tmr0h, is executed. on the other hand, using instructions to preload data into the high byte timer register will result in the data be- ing directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the 0
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ht37q70/60/50/40/30/20 rev. 1.00 32 february 17, 2009 high byte register must first be executed to latch the con - tents of the low byte buffer into its associated low byte register. after this has been done, the low byte register can be read in the normal way. note that reading the low byte timer register will only result in reading the previ - ously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control registers tmr0c, tmr1c, tmr2c the timer/event counters0/1 enable them to operate in three different modes. the options of which are deter - mined by the contents of their respective control regis - ter. there are four timer control registers, known as tmr0c, tmr1c and tmr2c. it is the timer control reg - ister together with its corresponding timer registers that control the full operation of the timer/event counters. before the timers can be used, it is essential that the ap - propriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. to choose which of the three modes the timer is to oper - ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair t0m1/t0m0, t1m1/t1m0 respectively, depending upon which timer is used, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as t0on, t1on or t2on, depending upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the coun- ter. if the timer is in the event count or pulse width mea- surement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as t0e, t1e or t2e, depend- ing upon which timer is used. configuring the timer mode in this mode, the timer can be utilized to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. to operate in this mode, bits tm1 and tm0 of the tmr0c~tmr2c register must be set to 1 and 0 respectively. in this mode, the internal clock is used as the timer clock. the input clock fre - quency of 16 bit timer to the timer is f osc /8 and rc12k, selected by tmr0c.5. the input clock frequency of 8 bit timer to the timer is fosc divided by the value pro - grammed into the timer prescaler, the value of which is determined by bits psc0~psc2 of the tmr1c~ tmr2c register. the timer-on bit, ton must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overflows, the timer will be reset to the value already loaded into the preload reg - ister and continue counting. if the timer interrupt is en - abled, an interrupt signal will also be generated. the timer interrupt can be disabled by ensuring that the et0i~et2i bit in the intc and intch registers is cleared to zero. it should be noted that a timer overflow is one of the wake-up sources. configuring the event counter mode in this mode, two number of externally changing logic events, occurring on external pin pa6/tmr0 or pa7/tmr1, can be recorded by the internal timer. for the timer to operate in the event counting mode, bits tm1 and tm0 of the tmr0c or tmr1c registers must be set to 0 and 1 respectively. the timer-on bit, ton must be set high to enable the timer to count. with te low, the counter will increment each time the pa6/tmr0 or pa7/tmr1 pin receives a low to high transition. if the te bit is high, the counter will increment each time pa6/tmr0 or pa7/tmr1 pin receives a high to low tran - sition. as in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and con- tinue counting. if the timer interrupt is enabled, an inter- rupt signal will also be generated. the timer interrupt can be disabled by ensuring that the eti bit in the intc and intch registers is cleared to zero. to ensure that the external pin pa6/tmr0 or pa7/tmr1 is configured to operate as an event counter input pin, two things have to happen. the first is to en - sure that the tm0 and tm1 bits place the timer/event counter in the event counting mode, the second is to en - sure that the share pin mr0 or tmr1 are selected by option. it should be noted that a timer overflow is one of the wake-up sources. also in the event counting mode, the timer/event counter will continue to record exter - nally changing logic events on the timer input pin, even if the microcontroller is in the power down mode. as a re - sult when the timer overflows it will generate a wake-up and if the interrupts are enabled also generate a timer interrupt signal.
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ht37q70/60/50/40/30/20 rev. 1.00 33 february 17, 2009 configuring the pulse width measurement mode in this mode, the width of external pulses applied to the pin-shared external pin pa6/tmr0 or pa7/tmr1 can be measured. in the pulse width measurement mode, the timer clock source is supplied by the internal clock. for the timer to operate in this mode, bits tm0 and tm1 must both be set high. if the te bit is low, once a high to low transition has been received on the pa6/tmr0 or pa7/tmr1 pin, the timer will start counting until the pa6/tmr0 or pa7/tmr1 pin returns to its original high level. at this point the ton bit will be automatically reset to zero and the timer will stop counting. if the te bit is high, the timer will begin counting once a low to high transition has been received on the pa6/tmr0 or pa7/tmr1 pin and stop counting when the pa6/tmr0 or pa7/tmr1 pin returns to its original low level. as be - fore, the ton bit will be automatically reset to zero and the timer will stop counting. it is important to note that in the pulse width measurement mode, the ton bit is au- tomatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the ton bit can only be reset to zero under program control. the residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin pa6/tmr0 or pa7/tmr1. as the ton bit has now been reset any further transitions on the pa6/tmr0 or pa7/tmr1 pin will be ignored. not until the ton bit is again set high by the program can the timer begin fur - ther pulse width measurements. in this way single shot pulse measurements can be easily made. it should be noted that in this mode the counter is controlled by logi - cal transitions on the pa6/tmr0 or pa7/tmr1 pin and not by the logic level. prescaler bits psc0~psc2 of the tmrc1~ tmrc2 registers can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. note: because the two timers are used by midi the ex - ternal timer pin functions are disabled. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quire the use of the external pa6/tmr0 or pa7/tmr1 pin for correct operation. as this pin is a shared pin it must be configured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode se - lect bits in the timer/event counter control register, se - lect either the event counter or pulse width measurement mode. additionally the pa share pin op - tion must be selected to ensure that the pin is setup as an tmr0 and tmr1 input. programming considerations when configured to run in the timer mode, the internal system clock f osc /8 is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not syn - chronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be a a - a 3 a 2
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a 3
a event counter mode timing diagram
ht37q70/60/50/40/30/20 rev. 1.00 34 february 17, 2009 small differences in measured values requiring pro - grammers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronized with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting er - ror, this should be taken into account by the program - mer. care must be taken to ensure that the timers are properly initialized before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal in - terrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corresponding in - terrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn gener - ate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the de - vice is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are en- abled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. show how to counter tmr0=1khz, tmr1=2khz, tmr2=4khz, if f osc is 11.059mhz. org 00h ; reset jmp begin org 04h ; external interrupt vector reti org 08h ; timer/event counter 0 interrupt vector jmp tmr0int ; jump here when timer0 overflows org 0ch ; timer/event counter 1 interrupt vector jmp tmr1int ; jump here when timer1 overflows org 10h ; timer counter 2 interrupt vector jmp tmr2int ; jump here when timer2 overflows org 20h ; main program ;internal timer0,1,2 counter interrupt routine tmr0int: ; timer/event counter 0 main program placed here : reti tmr1int: ; timer/event counter 1 main program placed here : reti tmr2int: ; timer counter 2 main program placed here : reti : begin: ; setup interrupt register
ht37q70/60/50/40/30/20 rev. 1.00 35 february 17, 2009 mov a, 0bh ; enable master interrupt, timer0 and timer1 interrupt mov intc,a mov a, 01h ; enable timer2 interrupt mov intch,a ;setup timer 0 registers mov a, low (65536-1382) ; setup timer preload low byte value, interrupt in 1khz mov tmr0l,a; mov a, high (65536-1382) ; setup timer preload high byte value mov tmr0h,a; mov a,080h ; setup timer 0 control register mov tmr0c,a ; timer mode and clock source is f osc /8 0.7234s set tmr0c.4 ; start timer - note mode bits must be previously setup mov a, low (256-173) ; setup timer preload value, interrupt in 2khz mov tmr1,a; mov a,080h ; setup timer 1control register mov tmr1c,a ; timer mode and prescaler output is f osc /32 2.89s set tmr1c.4 ; start timer - note mode bits must be previously setup mov a, low (256-173) ; setup timer preload value, interrupt in 4khz mov tmr2,a; mov a,080h ; setup timer2 control register mov tmr2c,a ; timer mode and prescaler output is f osc /16 1.447s set tmr2c.4 ; start timer - note mode bits must be previously setup interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter 0/1/2 or ercoci re- quire or an adpcm empty requires microcontroller at- tention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. each device in this series contains a single ex - ternal interrupt and two internal interrupts functions. the external interrupt is controlled by the action of the exter - nal int pin, while the internal interrupts are controlled by the timer/event 0/1counter overflow or ercoci re - quire or the adpcm empty interrupt. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by intc and intch registers, which are located in data memory. by controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding re - quest flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation timer/event 0/1/2 counter overflow, ercoci interrupt, adpcm empty request or the external interrupt line be- ing pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropri- ate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the correspond - ing interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.
ht37q70/60/50/40/30/20 rev. 1.00 36 february 17, 2009 2 3 ) * + ) ! h + d . d $ 6 ! $ : $ j . j 0 . +
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+ , ! + d . d $ interrupt low byte control register once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from oc - curring. however, if other interrupt requests occur dur - ing this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. in cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simulta - neously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the intc register can pre- vent simultaneous occurrences. interrupt source priority vector reset 1 00h external interrupt 2 04h timer/event counter 0 overflow 3 08h timer/event counter 1 overflow 4 0ch timer counter 2 overflow 5 10h ercoci interrupt 6 14h adpcm empty interrupt 7 18h external interrupt for an external interrupt to occur, the global interrupt en - able bit, emi, and external interrupt enable bit, eei, must first be set. an actual external interrupt will take place when the external interrupt request flag, eif, is set, a situation that will occur when a high to low transi - tion appears on the int line. the external interrupt pin is pin-shared with the i/o pin pa5 and can only be config - ured as an external interrupt pin if the corresponding ex - ternal interrupt enable bit in the intc register has been set. the pin must also be selected as by setting the cor - responding pac.5 bit in the port control register. when the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request flag, eif, will be automatically reset and the emi bit will be automatically cleared to dis- able other interrupts.
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ht37q70/60/50/40/30/20 rev. 1.00 38 february 17, 2009 timer/event counter interrupts for a timer generated internal interrupt to occur, the cor - responding internal interrupt enable bit must be first set. each device have two internal timer counters, the timer/event counter 0 interrupt enable is bit 2 of the intc register and known as et0i, the timer/event counter 1 interrupt enable is bit 3 of the intc register and known as et1i and the timer counter 2 interrupt enable is bit 0 of the intch register and is known as et2i. an actual timer/event counter interrupt will be ini - tialized when the timer/event counter interrupt request flag is set, caused by a timer overflow. each device has two timers, the timer/event counter 0 request flag is bit 5 of the intc register and known as t0f, the timer/event counter 1 request flag is bit 6 of the intc register and known as t1f, and the timer counter 2 re - quest flag is bit 4 of the intch register and is known as t2f. when the master interrupt global enable bit is set, the stack is not full and the corresponding timer interrupt en - able bit is set, an internal interrupt will be generated when the corresponding timer overflows. each device have two internal timer/event counters, a subroutine call to location 08h will occur for timer/event counter 0, a subroutine call to location 0ch for timer/event coun - ter 1, a subroutine call to location 10h for timer counter 2. after entering the timer interrupt execution routine, the corresponding timer interrupt request flag, either, t0f, t1f or t2f will be reset and the emi bit will be cleared to disable other interrupts. rc/f interrupt the external rc oscillation converter interrupt is initial- ized by setting the external rc oscillation converter in- terrupt request flag, rcocf; bit 5 of intch. this is caused by a timer a or timer b overflow. when the in - terrupt is enabled, and the stack is not full and the rcocf bit is set, a subroutine call to location
14h
will occur. the related interrupt request flag, rcocf, will be reset and the emi bit cleared to disable further interrupts. adpcm interrupt the internal adpcm interrupt is initialized by setting the adpcm interrupt request flag (adpcmf: bit 6, ch0f: bit 3 and ch1f: bit 7 of intch).the ch0f and ch1f set by adr0 or adr1 empty respectively. the adpcmf is set by adr0 or adr1 empty immediately. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 18h will occur. the related interrupt request adpcmf and ch0f/ch1f flag will be reset and the emi bit cleared to disable further interrupts. programming considerations the interrupt request flags t0f, t1f, t2f, adpcmf, ch0f, ch1f, together with the interrupt enable bits et0i, et1i, et2i, eadpcm, form the interrupt control registers intc, intch which are located in the data memory. by disabling the interrupt enable bits, a re - quested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will re - main in this condition in the intc or intch register until the corresponding interrupt is serviced or until the re - quest flag is cleared by a software instruction. it is rec - ommended that programs do not use the
call subroutine
instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con- trolled, the original control sequence will be damaged once a
call subroutine
is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the con- tents of the register or status register are altered by the interrupt service program, which may corrupt the de - sired control sequence, then the contents should be saved in advance.
ht37q70/60/50/40/30/20 rev. 1.00 39 february 17, 2009 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. + '

. > / '
power-on reset timing chart + . > ) . . * ' ' . > . ) . * enhanced reset circuit + ' ' . > ) . . * basic reset circuit
ht37q70/60/50/40/30/20 rev. 1.00 40 february 17, 2009 low voltage reset lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice, which is selected via a configuration option and the vlvr can select as 3.3v or 2.2v. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device in - ternally. the lvr includes the following specifica - tions: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. char - acteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera- tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to
1
. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to
0
and the to flag will be set to
1
. refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 0 1 res wake-up halt 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note:
u
stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal regis - ters of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. % '

low voltage reset timing chart "

wdt time-out reset during normal operation timing chart "

wdt time-out reset during power down timing chart +

. > / ' . > 2 '
res reset timing chart
ht37q70/60/50/40/30/20 rev. 1.00 41 february 17, 2009 ht37q70/60 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) tmr0h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1 0000 1 0000 1 uuuu u tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu rbp1 0 0 0 u rbp2 0 0 0 u bp1 xxx0 0000 xxx0 0000 xxx0 0000 xxx0 0000 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbmp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc 000 0000 000 0000 000 0000 uuu uuuu intch 1000 1000 1000 1000 1000 1000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 uuuu pdc 1111 1111 1111 uuuu dacc 0000 0 00 0000 0 00 0000 0 00 uuuu u uu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu chan 00 00 00 00 00 00 uu uu freqnh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu freqnl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu addrh xx xxxx uu uuuu uu uuuu uu uuuu addrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu reph xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu repl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu env x xxxx u uuuu u uuuu u uuuu
ht37q70/60/50/40/30/20 rev. 1.00 42 february 17, 2009 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) rvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0uuu adr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xspl 0000 0000 0000 0000 0000 0000 uuuu uuuu xsph 0000 0000 0000 0000 0000 0000 uuuu uuuu adpc 00 0 00 00 0 00 00 0 00 uu u uu adps 1111 1111 1111 uuuu ascr 0000 0000 0000 uuuu tmrah xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcoccr 0000 1 0000 1 0000 1 uuuu u tmrbh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcocr 00 00 00 uu note:
u
stands for unchanged
x
stands for unknown

stands for unimplemented
ht37q70/60/50/40/30/20 rev. 1.00 43 february 17, 2009 ht37q50/40 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) tmr0h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1 0000 1 0000 1 uuuu u tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu rbp1 0 0 0 u rbp2 0 0 0 u bp1 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbmp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc 000 0000 000 0000 000 0000 uuu uuuu intch 1000 1000 1000 1000 1000 1000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 uuuu pdc 1111 1111 1111 uuuu dacc 0000 0 00 0000 0 00 0000 0 00 uuuu u uu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu chan 00 00 00 00 00 00 uu uu freqnh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu freqnl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu addrh x xxxx u uuuu u uuuu u uuuu addrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu reph xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu repl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu env x xxxx u uuuu u uuuu u uuuu
ht37q70/60/50/40/30/20 rev. 1.00 44 february 17, 2009 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) rvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0uuu adr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xspl 0000 0000 0000 0000 0000 0000 uuuu uuuu xsph 0000 0000 0000 0000 0000 0000 uuuu uuuu adpc 00 0 00 00 0 00 00 0 00 uu u uu adps 1111 1111 1111 uuuu acsr 1 00 1 00 1 00 1 uu adrl xxxx xxxx xxxx uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 u1uu uuuu ascr 0000 0000 0000 uuuu tmrah xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcoccr 0000 1 0000 1 0000 1 uuuu u tmrbh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcocr 00 00 00 uu note:
u
stands for unchanged
x
stands for unknown

stands for unimplemented
ht37q70/60/50/40/30/20 rev. 1.00 45 february 17, 2009 ht37q30 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) tmr0h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1 0000 1 0000 1 uuuu u tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu rbp1 0 0 0 u rbp2 0 0 0 u bp1 xxxx x000 xxxx x000 xxxx x000 xxxx x000 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbmp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc 000 0000 000 0000 000 0000 uuu uuuu intch 1000 1000 1000 1000 1000 1000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 uuuu pdc 1111 1111 1111 uuuu dacc 0000 0 00 0000 0 00 0000 0 00 uuuu u uu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu chan 00 00 00 00 00 00 uu uu freqnh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu freqnl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu addrh xxxx uuuu uuuu uuuu addrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu reph xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu repl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu env x xxxx u uuuu u uuuu u uuuu rvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0uuu adr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ht37q70/60/50/40/30/20 rev. 1.00 46 february 17, 2009 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) xspl 0000 0000 0000 0000 0000 0000 uuuu uuuu xsph 0000 0000 0000 0000 0000 0000 uuuu uuuu adpc 00 0 00 00 0 00 00 0 00 uu u uu adps 1111 1111 1111 uuuu ascr 0000 0000 0000 uuuu tmrah xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcoccr 0000 1 0000 1 0000 1 uuuu u tmrbh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcocr 00 00 00 uu note:
u
stands for unchanged
x
stands for unknown

stands for unimplemented
ht37q70/60/50/40/30/20 rev. 1.00 47 february 17, 2009 HT37Q20 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) tmr0h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1 0000 1 0000 1 uuuu u tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu rbp1 0 0 0 u rbp2 0 0 0 u bp1 xxxx xx00 xxxx xx00 xxxx xx00 xxxx xx00 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbmp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc 000 0000 000 0000 000 0000 uuu uuuu intch 1000 1000 1000 1000 1000 1000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 uuuu pcc 1111 1111 1111 uuuu pd 1111 1111 1111 uuuu pdc 1111 1111 1111 uuuu dacc 000 00 000 00 000 00 uuu uu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu chan 00 00 00 00 00 00 uu uu freqnh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu freqnl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu addrh xxx uuu uuu uuu addrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu reph xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu repl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu env x xxxx u uuuu u uuuu u uuuu rvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0uuu adr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ht37q70/60/50/40/30/20 rev. 1.00 48 february 17, 2009 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) xspl 0000 0000 0000 0000 0000 0000 uuuu uuuu xsph 0000 0000 0000 0000 0000 0000 uuuu uuuu adpc 00 0 00 00 0 00 00 0 00 uu u uu adps 1111 1111 1111 uuuu ascr 000 000 000 uuu tmrah xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcoccr 0000 1 0000 1 0000 1 uuuu u tmrbh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcocr 00 00 00 uu note:
u
stands for unchanged
x
stands for unknown

stands for unimplemented
ht37q70/60/50/40/30/20 rev. 1.00 49 february 17, 2009 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. two types of system clocks can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. all oscillator options are selected through the configuration options. the two methods of generating the system clock are: external crystal/resonator oscillator external rc oscillator one of these two methods must be selected using the configuration options. more information regarding the oscillator is located in application note ha0075e on the holtek website. external crystal/resonator oscillator the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feed - back for oscillation, and will normally not require exter - nal capacitors. however, for some crystals and most resonator types, to ensure oscillation and accurate fre - quency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specifica - tion. the external parallel feedback resistor, rp, is nor - mally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25 c ca cb rf 7pf~9pf 9pf~11pf 300k oscillator internal component values external rc oscillator using the external system rc oscillator requires that a resistor, with a value between 82k and 180k , is con - nected between osc1 and vss. the generated system clock divided by 8 will be provided on osc2 as an output which can be used for external synchronization pur - poses. note that as the osc2 output is an nmos open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. although this is a cost effective oscillator configuration, the oscilla - tion frequency can vary with vdd, temperature and pro - cess variations and is therefore not suitable for applications where timing is critical or where accurate os - cillator frequencies are required. for the value of the ex- ternal resistor. note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of oscillation. - (
2 % ) % / - + / / ! + - 4 + - ! 6 d > ! < $ > - > # # # & - ! # , ! ! ( $ 0 ! ) > crystal/resonator oscillator - ( 6 ! external rc oscillator
ht37q70/60/50/40/30/20 rev. 1.00 50 february 17, 2009 watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 sat5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mode or sleep mode. when the device enters this mode, the nor - mal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consump - tion to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requir - ing a full reset. this feature is extremely important in ap - plication areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the
halt
instruc- tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the
halt
instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi - nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. this also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors con - nected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be re - quired if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac- tual source of the wake-up can be determined by exam- ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the
halt
instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual config - uration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up oc - curs, the program will resume execution at the instruc - tion following the
halt
instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the
halt
instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to
1
be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled.
ht37q70/60/50/40/30/20 rev. 1.00 51 february 17, 2009 no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the
halt
instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by one of two sources selected by con - figuration option: its own self contained dedicated inter - nal wdt oscillator or f osc /8. note that if the wdt configuration option has been disabled, then any in - struction relating to its operation will result in no opera - tion. the internal wdt oscillator has an approximate period of 65 s at a supply voltage of 5v. if selected, it is first di - vided by 256 via an 8-stage counter to give a nominal period of 17ms. note that this period can vary with vdd, temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maxi- mum time-out period of about 2.1s. a configuration option can select the instruction clock, which is the system clock divided by 8, as the wdtclock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a
halt
instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle
clr wdt
instruction while the second is to use the two commands
clr wdt1
and
clr wdt2
. for the first option, a simple execution of
clr wdt
will clear the wdt while for the second option, both
clr wdt1
and
clr wdt2
must both be executed to successfully clear the wdt. note that for this second option, if
clr wdt1
is used to clear the wdt, succes- sive executions of this instruction will have no effect, only the execution of a
clr wdt2
instruction will clear the wdt. similarly, after the
clr wdt2
instruc- tion has been executed, only a successive
clr wdt1
instruction can clear the watchdog timer. " - 5 6
) * + ) 0 . "
! " - . . . . " . . . . " . . . . . "
d d - d 2 d d d 3 - d 2 d - 6 $ " " . watchdog timer register
ht37q70/60/50/40/30/20 rev. 1.00 52 february 17, 2009 9 - 1 ; 0 7 i "

" . g " - "
* "

! ( ! % "
) % "
- ) - % % ( "
"
* ( ! watchdog timer 6 ) * + ) . + % 5 . 0 8 4 + % 5 + % " 4 + 6 4
$ ( & , . d ( 9 $ ( ; d ( & , + $ ( . d $ d 6 ! $ : $ j . j + $ $ ! & ! > ( . d $ d ( # $ ! & ! > . d d # . ( & , $ $ . d ( & , d ( $ $ # . ( & , $ $ . d ( & , d ( $ ! $ $ n $ ( - . d d - dacc (1fh) register note: *switch mp1and mp2 memory pointer by bp_r HT37Q20 don t contain bit2, bit3 and bit4 of dacc digital to analog converter (dacc) the two d/a converters of ht37q70/60/50/40/30/20 are 16-bit high-resolution with excellent frequency response char - acteristics and good power consumption for mono audio output. d7 d6 d5 d4 d3 d2 d1 d0 1dh dac high byte b15 b14 b13 b12 b11 b10 b9 b8 1eh dac low byte b7 b6 b5 b4 b3 b2 b1 b0 1fh dac control (dacc) bp_r selach1 selach0 amp_m amp_en dac selwr note: b15~b0 is d/a conversion result data bit msb~lsb.
ht37q70/60/50/40/30/20 rev. 1.00 53 february 17, 2009 the integrated power amp. the power amp. is an integrated class ab mono speaker driver contained in ht37q70/60/50/40/30.it provides property of high s/n ratio, high slew rate, low distortion, large output voltage swing, excellent power supply ripple rejection, low power consumption, low standby current and power off control etc. aud in: audio input v bias : speaker non-inverting input voltage reference sp+:audio negative output sp-: audio positive output outp rising time (t r ) when amp_en enable, the power amp. need rising time to output fully on outp pin. however, the rising time depends on. c1. (*the c1 connects with v bias and vss) - ' 8 . $ 8 a 4 + 6 m . > ) 5 4 + 6 7
capacitor 0.1f1 f 4.7f1 0 f t r voltage 2.2v 15ms 30ms 90ms 185ms 3v 15ms 30ms 90ms 185ms 4 15ms 30ms 90ms 185ms for battery based applications, power consumption is a key issue, therefore the amplifier should be turned off when in the standby state. in order to eliminate any speaker sound bursts while turning the amplifier on, the application circuit, which will incorporate a capacitance value of c1, should be adjusted in accordance with the speaker s audio frequency response. a greater value of c1 will improve the noise burst while turning on the amplifier. the recommended operation sequence is: turn on: audio signal standby (1/2vdd) enable amplifier wait t r for amplifier ready audio output turn off: audio signal finished disable amplifier wait t r for amplifier off audio signal off if the application is not powered by batteries and there is no problem with amplifier on/off issue, a capacitor value of 0.1 f for c1 is recommended. how to use integrated power amp? connect the
internal power amp circuit
, please refer to application circuits. set dacc.3 to enable integrated power amp. clear dacc.3 to disable integrated power amp. user can control it at
powerampdisable
and
powerampenable
of ht-mds. 5 4 + 6
ht37q70/60/50/40/30/20 rev. 1.00 54 february 17, 2009 music synthesis controller msc ch0~ch3 channel number selection each devices with integrated 4 channels output is se - lected by 2bits option and chan[1:0] is used to define which channel is selected. when this register is written to, the wavetable synthesizer will automatically output the dedicated pcm code. so this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined. change parameter selection these two bits, vm and fr, are used to define which register will be updated on this selected channel. there are two modes that can be selected to reduce the pro - cess of setting the register. please refer to the state - ments of the following table: vm fr function 0 0 update all the parameter 0 1 only change the frequency parameter 1 0 only change the volume parameter 1 1 unused output frequency definition the data on bl3~bl0 and fr11~fr0 are used to de- fine the output speed of the pcm file, i.e. it can be used to generate the tone scale. when the fr11~fr0 is 800h and bl3~bl0 is 6h, each sample data of the pcm code will be sent out sequentially. when the f osc is 11.059mhz, the formula of a tone fre- quency is: f out =f record x f / (16x8) sr x fr11 ~ fr0 2 osc (17 bl3~bl0) - where f out is the output signal frequency, f record and sr is the frequency and sampling rate on the sample code, respectively. so if a voice code of c3 has been recorded which has the f record of 261hz and the sr of 11025hz, the tone frequency (f out ) of g3: f out =98hz. can be obtained by using the formula: if fr=031h and bl=7, could get 98hz. 98hz= 261hz x 86.4khz 11.025khz x fr11 ~ fr0 2 (17 bl3~bl0) - bl3~bl0: range from 00h~0bh fr11~fr0: range from 000h~3ffh start address definition each device provides two address types for extended use, one is the program rom address which is program counter corresponding with bp1 value, the other is the start address of the pcm code. ht37q70/60 contains st13~st0 is used to define the start address of each pcm code and reads the wave - form data from this location. ht37q70/60 provides pcm 12/8 bit source pcm 12 start address definition pcm code has to be located at a multiple of 48 (byte) st12~st0= wa18~wa0/48 pcm 8 start address definition pcm code has to be located at a multiple of 32 (byte) st13~st0= wa18~wa0/32 ht37q50/40 contains st12~st0 is used to define the start address of each pcm code and reads the wave - form data from this location. ht37q50/40 provides pcm 12/8 bit source pcm 12 start address definition pcm code has to be located at a multiple of 48 (byte) st11~st0= wa17~wa0/48 pcm 8 start address definition pcm code has to be located at a multiple of 32 (byte) st12~st0= wa17~wa0/32 ht37q30 contains st11~st0 is used to define the start address of each pcm code and reads the waveform data from this location. ht37q30 provides pcm 12/8 bit source pcm 12 start address definition pcm code has to be located at a multiple of 48 (byte) st10~st0= wa16~wa0/48 pcm 8 start address definition pcm code has to be located at a multiple of 32 (byte) st11~st0= wa16~wa0/32 HT37Q20 contains st10~st0 is used to define the start address of each pcm code and reads the waveform data from this location. HT37Q20 provides pcm 12/8 bit source pcm 12 start address definition pcm code has to be located at a multiple of 48 (byte) st9~st0= wa15~wa0/48 pcm 8 start address definition pcm code has to be located at a multiple of 32 (byte) st10~st0= wa15~wa0/32
ht37q70/60/50/40/30/20 rev. 1.00 55 february 17, 2009 waveform format definition each device accepts two waveform formats to ensure a more economical data space. wbs is used to define the sample format of each pcm code. wbs=0 means the sample format is 8-bit (pcm8) wbs=1 means the sample format is 12-bit (pcm12) the 12-bit sample format allocates location to each sample data. please refer to the waveform format state - ment as shown below. repeat number definition the repeat number is used to define the address which is the repeat point of the sample. when the repeat num - ber is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80h) until the vol - ume become close. the re14~re0 is used to calculate the repeat address of the pcm code. the process for setting the re14~re0 is to write the 2 s complement of the repeat length to re14~re0, with the highest carry ignored. the ht37 will get the repeat address by adding the re14~re0 to the address of the end code, then jump to the address to repeat this range. volume control each device provides the volume control independently. the volume are controlled by vr9~vr0 respectively. the chip provides 1024 levels of controllable volume, the 000h is the maximum and 3ffh is the minimum out - put volume. the pcm code definition each device can only solve the voice format of the signed 8-bit or 12-bit raw pcm. and the mcu will take the voice code 80h as the end code. so each pcm code section must be ended with the end code 80h. 8 - 8 3 8 2 8 1 8 8 0 8 8 5 % - % - 5 - 3 5 3 ! $ $ o 8 $ > 8 - 8 3 % 6 d j 5 j 5 # 6 j j $ $ 6 j % j % & 6 ! $ $ name function d7 d6 d5 d4 d3 d2 d1 d0 20h channel number selection (chan) vm fr ch1 ch0 21h frequency number high byte (freqnh) bl3 bl2 bl1 bl0 fr11 fr10 fr9 fr8 22h frequency number low byte (freqnl) fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 23h start address high byte (addrh) st13 st12 st11 st10 st9 st8 24h start address low byte (addrl) st7 st6 st5 st4 st3 st2 st1 st0 25h repeat number high byte (reph) wbs re14 re13 re12 re11 re10 re9 re8 26h repeat number low byte (repl) re7 re6 re5 re4 re3 re2 re1 re0 27h control register (env) a_r env1 env0 vr9 vr8 28h 29h 2ah right volume control (rvc) vr7 vr6 vr5 vr4 vr3 vr2 vr1 vr0 wavetable register memory map (20h~2ah) adpcm address offset register name r/w default value description 30h adr w xxxx xxxx adpcm data register 31h xspl w 0000 0000 xn + sp initial register low byte 32h xsph w 0000 0000 xn + sp initial register high byte 33h adpc r/w 00x0 xx00 adpcm decoder control register 34h adps r 0000 1111 adpcm decoder status register ht-adpcm decoder registers
ht37q70/60/50/40/30/20 rev. 1.00 56 february 17, 2009 external rc oscillation converter an external rc oscillation converter is implemented in certain devices and is a function which allows touch switch functions to be implemented. when used in con - junction with the analog switch function up to eight touch switches can be implemented. external rc oscillation converter operation the rc oscillation converter is composed of two 16-bit count-up programmable timers. one is timer a and the other is counter known as timer b. the rc oscillation converter is enabled when the rco bit, which is bit 1 of the rcocr register, is set high. the rc oscillation con- verter will then be composed of four registers, tmral, tmrah, tmrbl and tmrbh. the timer a clock source comes from the f sys or f sys /4, the choice of which is determined by bits in the rcoccr register. the rc oscillation converter timer b clock source co- mes from an external rc oscillator. as the oscillation frequency is dependent upon external capacitance and resistance values, it can therefore be used to detect the increased capacitance of a touch switch pad. there are six registers related to the rc oscillation con - verter. these are, tmr2h, tmr2l, rcoccr, tmr4h, tmr4l and rcocr. the internal timer clock is the in - put clock source for tmrah and tmral, while the ex - ternal rc oscillator is the clock source input to tmrbh and tmrbl. the ovb bit, which is bit 0 of the rcocr register, decides whether the timer interrupt is sourced from either the timer a overflows or timer b overflow. when a timer overflow occurs, the rcocf bit is set and an external rc oscillation converter interrupt occurs. when the rc oscillation converter timer a or timer b overflows, the rcocon bit is automatically reset to zero and stops counting. the resistor and capacitor form an oscillation circuit and input to tmrbh and tmrbl. the rcom0, rcom1 and rcom2 bits of rcoccr define the clock source of timer a. when the rcocon bit, which is bit 4 of the rcoccr register, is set high, timer a and timer b will start count- ing until timer a or timer b overflows. now the timer counter will generate an interrupt request flag which is bit rcocf, bit 5 of the intch register. both timer a and timer b will then stop counting and the rcocon bit will automatically be reset to
0
at the same time. note that if the rcocon bit is high, the tmrah, tmral, tmrbh and tmrbl registers cannot be read or written to. ) * + ) 0 . 7 $ ( $ : $ = - . 6 , + d + . d
* - . . . d . . d . . . d ( b 9 ( - ; ( b 2 9 ( ; 7 $ ( $ d 7 $ ( $ rcoccr register 6
) * + ) . 0 . 4 + ! 4 + ! " 8 . 4 + ! " 8 4 + ! ' # . : + ! ) . d ! d ! ' # : + ! ) . d ! d ! ' # . : " 8 + ! ) . d ! d ! ' # : " 8 + ! ) . d ! d ! 6 ! $ : $ j . j adps (33h) adpcm status register
ht37q70/60/50/40/30/20 rev. 1.00 57 february 17, 2009 programming considerations as the 16-bit timers have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. it must be noted that when using in - structions to preload data into the low byte registers, namely tmral or tmral, the data will only be placed into a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely tmrah or tmrbh, is exe- cuted. however, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. after this has been done, the low byte reg- ister can be read in the normal way. note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. program example external rc oscillation converter mode example program timer a overflow: clr rcoccr mov a, 00000010b ; enable external rc oscillation mode and set timer a overflow mov rcocr,a clr intch.5 ; clear external rc oscillation converter interrupt request flag mov a, low (65536-1000) ; give timer a initial value mov tmral, a ; timer a count 1000 time and then overflow mov a, high (65536-1000) mov tmrah, a mov a, 00h ; give timer b initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b ; timer a clock source=f sys /4 and timer on mov rcoccr, a p10: clr wdt snz intch.5 ; polling external rc oscillation converter interrupt request flag jmp p10 clr intch.5 ; clear external rc oscillation converter interrupt request flag ; program continue

8
6 ' 8 c ' 8 c . + @ , ! 6 ! - * * 2 ) * + ) ! d
8 , ( & . d
, ( & , $ d + . d 0 . 7 $ ( $ : $ = 6 6 . rcocr register
ht37q70/60/50/40/30/20 rev. 1.00 58 february 17, 2009 analog switch there are 8 analog switch lines in the microcontroller for k0~k7 for ht37q70/60/50/40/30, except HT37Q20 which only have 4 analog switch lines for k0~k3 and the analog switch control register, which is mapped to the data memory. all of these analog switch lines can be used for touch key input keys.
> h > -
> h > 3
> h > 2
> h > 1
> h >
> h > 0 m . m m - m 3 m 2 m 1 m m 0 7

> h > 6
8
> h > analog switch
) * + ) & # 0 . m . : # ( ( m : # ( ( m - : # ( ( m 3 : # ( ( m 2 : # ( ( m 1 : # ( ( m : # ( ( m 0 : # ( ( ( ( : ( ( 7 $ ( $ : $ = 6 3 6 3 . . . . . . . . 6 - 6 6 . 6 - . . . . i 6 . . . . i 6 . . . . . i analog switch control register ascr
ht37q70/60/50/40/30/20 rev. 1.00 59 february 17, 2009 configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-mds software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. all options must be defined for proper system function, the details of which are shown in the table. no. function 1 watchdog timer: enable or disable 2 watchdog timer clock source: t1 (f osc /8) or rc osc 3 clrwdt instructions: 1 or 2 instructions 4 pa0~pa7: wake-up enable or disable (bit option) 5 pa, pb, pc and pd: pull-high enable or disable (port numbers are device dependent) 6 system oscillator: xtal mode or rc mode 7 lvr function: enable or disable lvr function: 3.3v/2.2v 8 share pin - pa5/int : enable (int )/disable (pa5) 9 r to f function : enable or normal i/o (pd) 10 r to f_ analog switch: enable or normal i/o (pc) k0 enable and pc1~7 k0~1 enable and pc2~7 k0~2 enable and pc3~7 k0~3 enable and pc4~7 k0~4 enable and pc5~7 k0~5 enable and pc6~7 k0~6 enable and pc7 k0~7 enable
application circuits note: if user has used internal power amplifier circuit, need to add two capacitances (47 f, 0.1 f) that be connected between vcca2 and vss. HT37Q20 can t apply the internal power amplifier circuit application because it don t integrated power amplifier. user need use external power amplifier circuit with HT37Q20.
*
in application circuit, the rch pin connect internal power amplifier circuit or external power amplifier circuit individually. ht37q70/60/50/40/30/20 rev. 1.00 60 february 17, 2009 . > ) + . . * ' . > ) ' ' 4 ' ' . 2 0 ) . > ) ' 4 ' 4 ! * 9 ; 2 0 ) . > ) ' - ' 4 1 . * ' . ) $ 4 n 5 ' a 2 % ) % / ! 7 ) 1 + - 4 + - 3 1 2 . > ) . ) 7
6 ' ' + ) + 7
6 m 9 ; 1 . * 7
6 7
0 ' 2 0 ) 5 8 9 ) % / ! 7 ) 1 + - 4 + ' + . . * ' . > ) ' ' 4 ' ' . ' 4 ' 4 2 0 ) . > ) ' ' 4 ' 5 ' m 9 ; 0 1 . * - > . 1 / 5 = '
ht37q70/60/50/40/30/20 rev. 1.00 61 february 17, 2009 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 11.059mhz sys - tem oscillator, most instructions would be implemented within 0.723 s and branch or call instructions would be implemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be
clr pcl
or
mov pcl, a
. for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht37q70/60/50/40/30/20 rev. 1.00 62 february 17, 2009 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the
set [m].i
or
clr [m].i
instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the
halt
in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht37q70/60/50/40/30/20 rev. 1.00 63 february 17, 2009 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the
clr wdt1
and
clr wdt2
instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both
clr wdt1
and
clr wdt2
instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc
and
[m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc
and
x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc
and
[m] affected flag(s) z ht37q70/60/50/40/30/20 rev. 1.00 64 february 17, 2009
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht37q70/60/50/40/30/20 rev. 1.00 65 february 17, 2009
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht37q70/60/50/40/30/20 rev. 1.00 66 february 17, 2009
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc
or
[m] affected flag(s) z ht37q70/60/50/40/30/20 rev. 1.00 67 february 17, 2009
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc
or
x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc
or
[m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht37q70/60/50/40/30/20 rev. 1.00 68 february 17, 2009
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht37q70/60/50/40/30/20 rev. 1.00 69 february 17, 2009
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht37q70/60/50/40/30/20 rev. 1.00 70 february 17, 2009
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht37q70/60/50/40/30/20 rev. 1.00 71 february 17, 2009
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht37q70/60/50/40/30/20 rev. 1.00 72 february 17, 2009
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc
xor
[m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc
xor
[m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc
xor
x affected flag(s) z ht37q70/60/50/40/30/20 rev. 1.00 73 february 17, 2009
package information 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 496 512 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht37q70/60/50/40/30/20 rev. 1.00 74 february 17, 2009 - . . 8 + ) p h 5
28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 697 713 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht37q70/60/50/40/30/20 rev. 1.00 75 february 17, 2009 - 1 2 8 ) p h 5 +
48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 ht37q70/60/50/40/30/20 rev. 1.00 76 february 17, 2009 2 - 1 - 2 8 ) p h 5 +
64-pin qfp (14mm 20mm) outline dimensions symbol dimensions in mm min. nom. max. a 18.8 19.2 b 13.9 14.1 c 24.8 25.2 d 19.9 20.1 e 1 f 0.4 g 2.5 3.1 h 3.4 i 0.1 j 1.15 1.45 k 0.1 0.2 0 7 ht37q70/60/50/40/30/20 rev. 1.00 77 february 17, 2009 1 1 - 2 - . 3 - 3 3 / 8 + ) h 5 q m
80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in mm min. nom. max. a 11.9 12.1 b 9.9 10.1 c 11.9 12.1 d 9.9 10.1 e 0.4 f 0.16 g 1.35 1.45 h 1.6 i 0.1 j 0.45 0.75 k 0.1 0.2 0 7 ht37q70/60/50/40/30/20 rev. 1.00 78 february 17, 2009 . 2 2 . . - . - 8 + ) h 5 q m
product tape and reel specifications reel dimensions sop 20w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.00.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 32.2 +0.3/-0.2 t2 reel thickness 38.20.2 ht37q70/60/50/40/30/20 rev. 1.00 79 february 17, 2009 8

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carrier tape dimensions sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ht37q70/60/50/40/30/20 rev. 1.00 80 february 17, 2009 " . + ) m . 8 . . ! * ! $ # # $ # $ > 5
ssop 48w symbol description dimensions in mm w carrier tape width 32.00.3 p cavity pitch 16.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 14.20.1 d perforation diameter 2 min. d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 12.00.1 b0 cavity width 16.20.1 k1 cavity depth 2.40.1 k2 cavity depth 3.20.1 t carrier tape thickness 0.350.05 c cover tape width 25.50.1 ht37q70/60/50/40/30/20 rev. 1.00 81 february 17, 2009 . + ) m - 8 . . " m ! * ! $ # # $ # $ > 5 9 ; 5 9 + ! ;
ht37q70/60/50/40/30/20 rev. 1.00 82 february 17, 2009 copyright 2009 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) g room, 3 floor, no.1 building, no.2016 yi-shan road, minhang district, shanghai, china 201103 tel: 86-21-5422-4590 fax: 86-21-5422-4705 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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